Demo: More Than Point Tools: RISC-V Solutions
Talkat RISC-V Summit North America 2024 · on Tuesday, 2024-10-22· at 13:05· Expo Hall - Exhibit Hall A - Demo Theater·
summary
Synopsys presents a full RISC-V flow: formal model checking and assertion IP covering the ISA, dynamic verification with the Imperas FPM reference model (supporting 152 extensions and custom ops), Emperis DV co‑simulation plus Sting test generation and prebuilt test suites, Virtualizer virtual prototypes that hit 500 million instructions per second and boot Linux in about six seconds, HAPS FPGA prototyping and Zebu emulation, ARC5 processor IP families (ARC5 processor IP) and ASIP Designer with 12 example accelerator templates.
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chapters (11)
- 0:00Introduction and overview
- 1:07Synopsys RISC-V solutions range
- 2:12Formal verification tools
- 2:53Dynamic verification models
- 3:55Co-simulation environment
- 5:00Test generation tools
- 6:04Virtual prototyping
- 7:51FPGA prototyping and emulation
- 8:33RISC-V specific IP
- 9:37Custom accelerator design
- 10:21Summary and ecosystem support
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