RISC-V RAS Error-Record Register Interface (RERI)

on YouTube ↗19m

" summary

RERI is a ratified register interface that standardizes per-component memory-mapped error registers grouped into configurable error banks with headers and self-consistent records that log corrected vs uncorrected, deferred (poisoned) and critical errors. It exposes corrected-error counters configurable for when to signal software, supports error-injection delay counter (clock cycles or retired-instruction based) to exercise software handlers, signals via IRQs or richer reporting networks, and coexists with existing frameworks like PCIe while remaining extensible for functional-safety uses.

AI-written summary · about

" chapters (8)

1. 0:00Introduction to RERI
2. 1:25What is RERI standard
3. 5:20Error record structure
4. 9:14Handling multiple errors
5. 10:19Error injection testing
6. 12:03Software integration
7. 13:47Flexibility and extensibility
8. 14:31Q&A session

" related talks

• 39mReliability Availability and Serviceability (RAS) on LinuxMauro Carvalho Chehab · LinuxCon + CloudOpen Europe 2013
• 22mEnhancing RISC-V Performance Analysis InfrastructureAtish Patra, Beeman Strong · RISC-V Summit North America 2023
• 16mPerf feature improvements in RISCVAtish Patra · Linux Plumbers Conference 2023
• 16mProcessor Trace in a Holistic WorldCiprian Pascu · 8th RISC-V Workshop Barcelona 2018
• 32mDebug SpecificationGajinder Panesar · 8th RISC-V Workshop Barcelona 2018
• 18mAI-Ready RISC-V Using On-Chip Monitoring for Performance & Reliability at ScaleZ. Paz, M. Evans · RISC-V Summit North America 2025
• 25mRISC-V Zkt: Portable Timing Attack Resistance (via Dynamic Taint Analys...Markku-Juhani O. Saarinen · RISC-V Summit 2022
• 19mAdvance the Performance Analysis on RISC-Vfei wu, Jiangang Duan · RISC-V Summit 2022