Say Goodbye to Fear, Uncertainty, and Doubt: Innovate with Codasip Studio Fusion
Talkat RISC-V Summit North America 2024 · on Tuesday, 2024-10-22· at 11:30· Grand Ballroom G (Level 1)·
summary
Codasip Studio Fusion pairs formally verified L110/L730 cores with a workflow for bounded customization that adds custom instructions without breaking formal verification. A demo on 40 nm with a small M0-sized core shows a >4x efficiency boost, >6x power reduction at 25 MHz, and inner-loop neural GMM acceleration up to 16x versus a baseline RISC‑V C implementation; an FFT benchmark uses ARM/CMSIS library ports and intrinsics to expose DSP extensions for L110, proving portability and compiler/library paths.
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chapters (7)
- 0:00Introduction to disruptors
- 1:04Demo of core customization
- 3:12Removing fear uncertainty and doubt
- 4:14Bounded customization explained
- 7:45Software abstraction with libraries
- 11:23Balancing innovation and risk
- 12:06Q&A session
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