SiFive Event Trace: The First Zero-Overhead Performance Tool for RISC-V Processors

on YouTube ↗15m

" summary

SiFive Event Trace is a hardware feature that injects call/return, exception, interrupt, watchpoint and trigger messages into the RISC-V ENTRACe stream so profiling runs on production code with zero-overhead. Each trace message carries high-resolution timestamps and associated program counters; on-event counters are reset so you get delta performance counters (cache misses, branch mispredicts, instruction counts) between events. Filters support privilege modes and PIDs to limit trace traffic. Tooling integrates with Freedom Studio and Trace Compass and runs on SiFive HiFive boards.

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" chapters (7)

1. 0:00Introduction to challenges
2. 1:34SiFive event trace overview
3. 4:10Performance profiling counters
4. 7:05Collaboration and tools
5. 8:43Practical tools and demo
6. 12:02Summary and benefits
7. 12:56Q&A session

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