Debugging on Homogeneous and Heterogeneous Multicore SoCs w/ RISC V

on YouTube ↗10m

" summary

An Eclipse-based environment from Ashling claims to debug heterogeneous multicore SoCs (RISC-V SweRV plus Synopsys ARC on a Xilinx FPGA) using a single physical probe, supporting JTAG cJTAG and CoreSight SWD and configurable via XML. It demonstrates Eclipse-based environment that runs system-wide breakpoints and lockstep control, shares one probe across cores, and shows live register, source, and launch views per core. The demo on FPGA reportedly works end-to-end.

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" chapters (7)

1. 0:00Intro
2. 0:29System-on-Chip (SOC) Design Trends
3. 2:11RISC-V + ARM SOC Example
4. 4:12Too Many Tools!
5. 6:14RiscFree Debug Launch Settings
6. 7:12RiscFree Debug View Showing Multiple Launches
7. 9:28Conclusion

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