State of the Union

on YouTube ↗36m

" summary

Project begins in 2010; a 64‑bit core tapes out in 28nm FD‑SOI 2011 tape-out and Rocket Chip ships by 2012, the Foundation forms in 2015, NVIDIA picks RISC‑V for GPU controllers in 2016 and SiFive ships the FE310 microcontroller the same year, Western Digital commits in 2017. The formal spec moves to SAIL formal spec with compliance tests, the vector extension targets a mid‑2020 freeze, governance adds task groups and a CTO role, and an analyst report forecasts 62 billion RISC‑V cores in five years.

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" chapters (22)

1. 0:00Intro
2. 2:14RISC-V Timeline
3. 4:33What's Different about RISC-V?
4. 5:20RISC-V Ecosystem
5. 7:24Why is RISC-V so popular?
6. 12:20Fragmentation versus Diversity
7. 13:29How we structure RISC-V standards
8. 14:33ISA modules Linux 2017 Linux 2020
9. 18:51How is RISC-V Avoiding Fragmentation?
10. 22:00Special Interest Groups
11. 23:03Standards Process
12. 25:08R4 Foundation Board of Directors' Award 2019
13. 26:13"B" Bit-Manipulation Extension
14. 26:32"V" Vector Extension
15. 28:17Fast Interrupts "CLIC" Task Group
16. 28:42Privileged Architecture 1.12
17. 30:50Discovery Mechanism
18. 31:09Embedded ABI
19. 31:36Floating-Point Updates, New TG
20. 32:06New Priv-Arch TG Proposals
21. 32:22Call for Standards Participation
22. 33:04Summary

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