Keynote: RISC-V State of the Union

on YouTube ↗20m

" summary

RISC‑V claims clear momentum: entrenched in embedded, adopted as the default for new AI accelerators, and gaining traction in automotive and server spaces with Android support progressing. Profiles and cadence aim to reduce fragmentation: RVA23.1 adds five supervisor options with three tagged as development options (reserve bits double trap counter delegation) and two as expansion options (control transfer records QoS IDs). DSP support advances — P extension nears ratification — and four competing matrix approaches (ZV A, IME, VME, AM) pursue hardware/software tradeoffs for AI performance.

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" chapters (3)

1. 0:00State of the RISC-V union
2. 1:43Vertical market strategies
3. 5:04Technical and AI roadmaps

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