RISC-V Customization After a Tape-out
summary
Demonstration shows post-tape-out ISA extension by mapping a new RISC-V custom instruction into an on-chip e-FPGA, using Codasip L110 plus Studio (kodal → RTL, SDK, LLVM-aware compiler) and Menta Origami (RTL → bitstream). A 2×2 matrix-multiply instruction compiles automatically, uses ~12.7% logic and ~75% of 12 DSPs, and yields growing cycle savings as matrix size increases. Tooling produces RTL, testbenches, and back-annotated timing for quick iterations and field reprogramming. L110 Studio Origami 12.7% logic 75% DSP
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chapters (9)
- 0:00Introduction
- 1:25Business case for customization
- 3:10Solution components overview
- 4:35EFPGA technology explained
- 7:05Integration with RISC-V core
- 9:09High-level custom instruction design
- 11:59Case study matrix multiplication
- 14:54Conclusions and future work
- 16:41Q&A session
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