Demo: More Than Point Tools: RISC-V Solutions
summary
Synopsys presents a full RISC‑V stack claim backed by numbers not marketing fluff: ASIP Designer and Platform Architect for architecture exploration, the Imperius FPM reference model reused by 150 organizations and enabling over 50 RISC‑V SoC tapeouts, Empirus DV plus the Sting constrained‑random test generator for RTL and emulator runs, Virtualizer for early software bringup, and HAPS/Zebu for FPGA prototyping and emulation. Also offers ARC‑based RMX/RHX/RPX processor IP families with ISO‑26262 and ISO‑21434 options and professional services.
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chapters (6)
- 0:00Introduction to RISC-V solutions
- 1:47Architecture exploration tools
- 3:54Verification solutions
- 7:08Virtual prototyping and software
- 10:44Hardware platforms and IP
- 12:52Synopsys RISC-V portfolio summary
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