RISC-V Performance Delivered
summary
Claims a RVA23-compliant 8-core test chip with high-end OoO cores and an in-order AI core, taped out in months and sampling Q2 next year. Cores hit 4+ GHz class clocks and support up to four-way SMT, yielding typical SMT speedups of ~1.2–1.3 and outliers at 2x–3x for certain database and data‑movement workloads. End-to-end stack includes AXI/CHI interconnects, matrix‑multiply accelerators, FPGA and Palladium emulation, and zero-cost external profiling plus 250+ apps already run on FPGA.
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chapters (8)
- 0:00Introduction and overview
- 2:03High performance RISC-V cores
- 5:59Alpine test chip details
- 8:27SMT performance benefits
- 10:39Full product portfolio
- 13:11Scalability and AI solutions
- 15:38System modeling and emulation
- 17:24Performance tuning focus
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