RISC-V System-level Certification from Verification Foundations
summary
Covers concrete system-level tests and a toolchain that synthesizes C+ASM tests and TBX testbenches from graph models, exercising atomics, cache coherency, AIA (MSIC/APLIC) interrupts, MMU/IOMMU and IOPMP. Uses randomized AIA configs, free‑running loops with ~50 agents to force arbitration, and end‑of‑test checks for dropped or duplicate interrupts. Claims automated coverage over a ~10^140 search space filtered to realistic paths, implements test-suite synthesis and MSIC/APLIC message-signaled interrupts, runs real‑time in sim/emul and postprocesses FPGA/post‑silicon traces.
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chapters (14)
- 0:00Introduction and speaker background
- 1:07System-level certification challenges
- 3:39Atomics and memory consistency
- 5:07Advanced Interrupt Architecture
- 7:33Virtualization and IOMMU
- 9:21Debug and trace systems
- 12:46Coherency verification strategies
- 15:35AIA use cases and trade-offs
- 16:39Breker's test synthesis approach
- 17:20MMU and page mapping tests
- 18:44AIA test case generation
- 20:32Debug and coverage tools
- 23:01Test plan integration and coverage
- 24:03Q&A on debugging methods
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