Demo: XuanTie High-Performance Processors with Continuous Innovation and Iteration
summary
C930 is a ground-up microarchitecture claiming six decode and 16 stage pipeline with aggressive front end and full MMU features including nested translation and dynamic TSO, targeting >3.4 GHz. It offers per-core 512-bit vector units plus a shared matrix/tensor accelerator (up to six cores sharing, 512-bit vector and 408 TOPS matrix) and platform pieces: XL300 coherent interconnect (8-core, Xlink 300 up to 32 MB L3), DSA co‑processor interface with Cell/JSON toolchain that generates simulator/compiler/assembler, and reliability targets around 1e-18 UBER.
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chapters (10)
- 0:00Introduction to XuanTie processors
- 1:50C series flagship product 930
- 4:41Coherent interconnect XLink 300
- 10:58Vector and matrix design in 930
- 12:47Assist solutions and interconnect
- 16:00Distributed MMU and IO virtualization
- 17:47Software stack and RA solution
- 19:17Security and SMT features
- 19:37ShenTie DSA co-processor
- 20:41Product line summary and Q&A
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