Tiling Support in the SiFive AI/ML Software Stack for RISC-V Vector-Matrix Extension (VME)
summary
SiFive adds multi-tile matmul support to its IREE-based AI/ML stack that targets the RISC-V Vector-Matrix Extension (VME). VME uses an outer-product tile register state and exposes runtime M/N/K knobs so tiling fits varied bitwidths and batch sizes; K can pack 1–4. The new path implements multi-tile (4x) matmul that computes four tiles together, reorders loops to make K the outer loop, and reduces memory bandwidth on SiFive Intelligence XM matrix engines with surrounding X300 cores, yielding higher arithmetic density and reuse.
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chapters (7)
- 0:00Introduction to talk
- 0:41VME and tiling basics
- 3:10Tiling implementation details
- 5:44SiFive AI/ML software stack
- 7:09ERIE compiler framework
- 8:36Multi-tile support benefits
- 10:24Summary and Q&A
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