~/talk

Next-Generation Edge AI with RISC-V Vector Cores for Vision Applications

Talkat RISC-V Summit North America 2025 · 2025-10-22..10-23· [machine-learning]
links:none on file
slides:none on file

RISC‑V vector cores are integrated as two programmable vector engines of 2x8 CVA6V cores with 2MB scratchpad each that move 2D image data locally to avoid PCIe copy stalls and host preprocessing bottlenecks. A 4K vector length, 1.2 GHz operation and dedicated DMAs enable on‑chip pre/postprocessing and midprocessing for vision pipelines, claiming 16 Full HD streams at 30 fps on chip and per‑card performance that beats a mobile GPU core for NMS while the Europa line peaks at up to 629 TOPS at 45 W.

AI-written summary · about

  1. 0:00Introduction and context
  2. 1:32Challenges in edge AI
  3. 3:42Evaluating design options
  4. 5:37RISC-V vector architecture
  5. 7:53Introducing Europa
  6. 10:46Performance benchmarks
  7. 12:31Software stack and roadmap
  8. 15:24Q&A and closing remarks
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