Demo: From Blueprint to Reality: Navigating SoC Tradeoffs, IP, and Ecosystem
summary
Emphasizes early architecture modeling and asks for instruction‑accurate and cycle‑accurate models plus SystemC to verify performance before silicon; recommends FPGA/emulation because tapeout alone can cost ~$10M and full SoC programs hit $30–200M. Describes an ACE sandboxed custom extensions flow that adds custom ops or coprocessors, injects a C/SystemC golden model into the CPU model, and wires intrinsics into GCC so custom matrix engines move data via RV loads/stores and run in the simulator.
AI-written summary · about
chapters (9)
- 0:00Introduction and overview
- 1:02SOC development challenges
- 3:27Hardware-software tradeoffs
- 4:10Processor IP selection criteria
- 6:15Customizing processor IP
- 7:41IP deliverables and quality
- 10:36Software ecosystem for RISC-V
- 12:45Early collaboration with IP vendors
- 14:53Q&A session
related talks
11mDemo: Andes ACE: Enabling Custom RISCV Instructions Safely
15mA Pre-silicon Development & Analysis for SOAFEE to Accelerate Product Development
21mSoftware Flow for Complex SoC FPGA
49mFPGA: creating hardware by programming
11mDriving SoC Innovation with Synopsys RISC-V Solutions
20mVirtual Prototypes and Open Source Hardware Design in Research and Education
15mKeynote: Co-Designing Software and Hardware: Pillars of Advancing RISC-V for Application Success
42mIntroduction to SoC+FPGA