Driving SoC Innovation with Synopsys RISC-V Solutions
summary
Synopsys outlines specific RISC-V offerings: an ASIP tool generates SDK and RTL for custom processors and early exploration, Imperas Fast processor models for virtual prototyping and processor verification, and emulation/prototyping on HAPS and Zebu. The Arc five portfolio contains RMX small embedded cores, RHX real-time 32-bit dual-issue 10-stage RHX up to 16 cores with hardware virtualization, and RPX 64-bit host cores for Linux. DSO doAI automated flow reaches a 1.95 GHz target while meeting ~30 mW power goals.
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chapters (8)
- 0:00Introduction to RISC-V at Synopsys
- 1:03Market trends driving RISC-V adoption
- 2:30ASIP tools for custom processor design
- 3:35Arc5 processor portfolio overview
- 6:42Emulation and prototyping for RISC-V
- 7:48AI-enhanced design space optimization
- 9:14Synopsys RISC-V ecosystem integration
- 10:21Closing and Q&A invitation
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