~/talk

The European Accelerator (EPAC) demonstrator with 3 RISC-V based accelerators

Talkat RISC-V Summit Europe 2024 · 2024-06-24..06-28
links:none on file
slides:none on file

A taped-out RISC-V chip includes three accelerators (VTI scalar core + wide VPU, VRP, SDX) and boots standard Ubuntu Linux from a companion FPGA that provides DDR over a high-speed link because there is no on-chip memory controller. The demo runs a sparse matrix–vector kernel on a single 300 MHz core and shows 18x speedup when offloading to the VPU, which implements 256 double-precision lanes per vector instruction, with caches and NoC integrated and silicon fabricated and running on the demo board.

AI-written summary · about

  1. 0:00Introduction and background
  2. 1:25European Processor Initiative overview
  3. 2:53EPAC demonstrator hardware setup
  4. 5:40Linux boot and system setup
  5. 7:46Demo of sparse matrix-vector multiplication
  6. 10:02Conclusion and booth invitation
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