TETRISC SoC, an fault-tolerant and adaptive quad-core system

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" summary

A quad-core RISC-V SoC is a fault-tolerant, self-adaptive system taped out in 130 nm that converts an ETH Zurich single‑core design into four cores and adds an on‑chip sensor suite including an SRAM radiation counter, two aging monitors and an analog temperature sensor feeding a central sensor‑framework controller. Runtime policy trades off reliability, performance and power; one core uses TMR full hardening while another uses AI‑guided selective hardening. A live demo of automatic core replication and fault injection fails onstage, with planned laser and heavy‑ion testing next.

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" chapters (6)

1. 0:00Introduction to TETRISC SoC
2. 1:55Project goals and approach
3. 3:21On-chip sensors and monitoring
4. 6:11Live demo and fault injection
5. 7:35Future enhancements and open source
6. 9:42Q&A and conclusion

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