Developing a RISC-V Automotive Safety Island
summary
Proposes a physically isolated on-chip safety island that runs RISC-V real-time CPU cores in lockstep with ECC-protected TCMs, its own interconnect, clocks and power rails, and a deterministic memory subsystem. Claims ASIL D functions (ABS) and safety monitoring live there while ASIL B and infotainment run on a separate high-performance domain; shared buffers are tightly configured by the safety software and all external data is treated as untrusted.
AI-written summary · about
chapters (5)
- 0:00Introduction
- 1:09Automotive industry trends
- 5:00Functional safety in automotive
- 10:21Safety Island concept
- 16:37Summary and conclusion
related talks
20mThe Challenges in Supporting Multiple Safety Levels in the Same System
16mAutomotive Solution Empowered by RISC-V Based Security and Functional Safety Module
11mKeynote: Shaping the Future of Automotive Computing with RISC-V
20mThe Application of RISC-V Extensions to Automotive Zonal Controllers
21mRISC-V and Functional Safety
20mIntegrate RISC V to build Open Common Automotive Platform
09mDemo: Enabling Automotive Safety with Andes RISC-V IP
12mDemo: Andes Technology RISC-V Functional Safety Solutions