Demo: Andes Technology RISC-V Functional Safety Solutions

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" summary

Andes presents certified RISC‑V cores targeted at automotive ASIL-B to ASIL-D use: N25 FSE and D25 FSE are 32‑bit, five‑stage in‑order single‑issue cores with RV32GC (D25 adds P for packed DSP), D45 SE is a dual‑issue core with 2–3× memory throughput via M‑boost, and D45 supports dual lockstep for higher diagnostic coverage. Cores expose a core trap/status SP interface, a safe local‑memory port, common bus (AXI/AMBA) support, and certification timelines from late‑2023 through 2025.

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" chapters (7)

1. 0:00Introduction to functional safety
2. 2:08Automotive industry challenges
3. 3:31Safety design requirements
4. 6:18Andes safety solutions roadmap
5. 8:07Core architecture highlights
6. 9:56High-performance safety core
7. 11:40Product portfolio summary

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