~/talk

Open-Source HW Commercial Adoption: Lessons Learned

Talkat RISC-V Summit North America 2023 · on Tuesday, 2023-11-07· at 12:10· Theater (Level 2)· [open-source]
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CORE-V family is SystemVerilog IP with auditable, pre-silicon functional verification and open-source testbenches that run on Cadence Synopsys and Siemens toolchains; repositories show 1,600 forks, 4,000 stars and verification recipes. Licensing uses Apache + SolderPad license to enable commercial use. Outcomes include 40+ tape-outs for embedded cores and ~40 tape-outs for application cores, hundreds of millions of shipped units claimed, a taped-out microcontroller on GlobalFoundries 22FDX, and vendor-neutral FPGA/AWS F1 bitstreams plus a CI platform.

AI-written summary · about

  1. 0:00Introduction and handover
  2. 1:32Open Hardware overview
  3. 4:02Industrial adoption journey
  4. 8:14Permissive license importance
  5. 11:52Verification and trust
  6. 13:17Building the ecosystem
  7. 15:46Vendor-neutral testing platform
  8. 16:49Q&A and closing remarks
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