Demo: NEOX TM : An Ultra-Low Power RISC-V GPGPU Enabling 3D & TinyML

on YouTube ↗10m

" summary

NEOX is a RISC-V GPGPU claiming native 3D and TinyML on MCUs: RV64IMFC cores with custom SIMD and AI instructions, up to 32 threads per core and scalable to four cores, delivering tile-based rendering and on-chip rasterizer with 4x4 matrix transforms. Runtime and offline AI-SDK integrates with TFLite Micro, plus image compression tools (4/6/12 bpp) and an FPGA demo rendering glTF models on a single core at 50 MHz. Power target around 5 mW and shipped toolchain includes RV64IMFC ISA support and glTF 3D on a single-core FPGA at 50 MHz.

AI-written summary · about

" chapters (5)

1. 0:00Introduction to Neox GPGPU
2. 2:34Neox architecture and features
3. 5:43Software tools and ecosystem
4. 7:083D graphics with glTF
5. 9:17Summary and Q&A

" related talks

• 20mCould RISC-V Become a Force in HPC?Niraj Dengale · RISC-V at embedded world 2024
• 07mDemo: Neural Network Acceleration on Metis, Powered by RISC-VFlorian Zaruba, Victor Labian Carro · RISC-V Summit North America 2025
• 14mRISC-V Grows Up and Goes Big!John Min · RISC-V Forum: Embedded Technologies 2021
• 18mRISC-V Performance DeliveredRabin Sugumar · RISC-V Summit North America 2025
• 02mRISC-V WelcomeKim McMahon · RISC-V Forum: Embedded Technologies 2021
• 17mRISC-V Meets 22FDX: an Open Source Ultra-low Power Microcontroller PlatformPasquale Davide Schiavone, Sanjay Charagulla · 8th RISC-V Workshop Barcelona 2018
• 22mKeynote: RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billions of ProcessorsFrans Sijstermans · RISC-V Summit North America 2024
• 40mHands-on TinyML Deployment on RISC-V: Building an Optimized Edge AI Pipeline - Corrected AudioYueh-Feng Lee, Niraj Dengale · RISC-V Summit Europe 2026 Developer Workshops