SIMD Everywhere Optimization from ARM NEON to RISC-V Vector Extensions

on YouTube ↗17m

" summary

Enhanced SIMDe converts ARM NEON intrinsics to RISC‑V V-extension intrinsics and C‑level vectors, implements customized per-function translations, and adds a fixed-size RVV attribute so RVV types can live in global unions. Conversion reaches about 57% conversion coverage of NEON instructions and uses RVV intrinsics where available; tested on XNNPACK and OpenCV and yields 1.51–5.13× speedup over unmodified SIMDe. Remaining issues include redundant vset emissions and missed cross‑lane aggregation for long RVV lengths; SIMDe is the tool used.

AI-written summary · about

" chapters (12)

1. 0:00Introduction to SIMD
2. 1:00SIMD Everywhere overview
3. 2:20Project contributions
4. 3:11Technical design challenges
5. 5:56Function conversion strategy
6. 6:41Intrinsic mapping examples
7. 9:40Implementation example
8. 10:18Experimental results
9. 11:40Performance issues
10. 12:58Ongoing optimization work
11. 14:06Conclusion and Q&A
12. 15:03Industry application

" related talks

• 19mAggregation Optimization for SIMD Everywhere from ARM Neon to RISC-V Vector and Crypto ExtensionsJenq-Kuen Lee, Hung-Ming Lai · RISC-V Summit North America 2024
• 15mPushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC...R. Fuhler · RISC-V Summit North America 2025
• 17mRecent Developments in Optimizing Compilers for RISC-VJeff Law · RISC-V Summit North America 2025
• 19mGetting the Most out of the LLVM Auto Vectorizer for RISC-V Vectors (RVV)Kolya Panchenko · RISC-V Summit 2022
• 10mAn Introduction to RISC-V Vector Programming with C IntrinsicsChih-Mao Chen · RISC-V Global Forum 2020
• 16mImprovements to RISC-V Vector code generation in LLVMAlex Bradbury, Luke Lau · RISC-V Summit Europe 2025
• 28mLLVM for RISCVAlex Bradbury · 8th RISC-V Workshop Barcelona 2018
• 23mCode Size of RISC V versus ARM using the Embench™ 0 5 Benchmark SuiteDavid Patterson · RISC-V Summit 2019