LLVM for RISCV

on YouTube ↗28m

" summary

Describes adding bit-manipulation ops to the LLVM RISC-V backend with working RV32 and RV64 support now upstream, claiming parity with GCC for code size on the sponsor's workload and ongoing atomic lowering. Demonstrates a prototyped .insn assembler directive for quick experiments, full assembler support via tablegen patterns and SelectionDAG matching, lit tests for round trips, llc debug tracing, a ~12 GB debug clang/LLVM build and iterative ~30 s edit/compile cycles.

AI-written summary · about

" chapters (6)

1. 0:00Introduction to LLVM for RISC-V
2. 5:27Compiler setup and toolchain
3. 10:45Adding assembler support
4. 17:02Implementing instruction selection
5. 23:00Debugging and testing
6. 26:53Resources and next steps

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