RISC V Bit Manipulation ISA Extension Spec, Hardware, Software
summary
Adds concrete instructions and shows measured wins: min/max gave 4× speedup on an inner HMMER Viterbi loop by removing a branch, reference Verilog cores report gate counts and timing versus Rocket multiply/divide, and toolchain support exists in Spike, LLVM/GCC intrinsics and binutils. Proposes optional ternary ops for compact code, bit-permutation/shuffle primitives (zip/unzip, generalized shuffle), bit-matrix ops for 64×64 blocks, and crypto/CRC work with carryless multiply ≈1 instr/byte CRC improvements in benchmarks.
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chapters (23)
- 0:00Start
- 0:05Min and Max Instructions
- 2:40Ternary Instructions
- 4:36Expansion and Fusion
- 8:08Low-Level Idioms
- 12:43Reference Implementations
- 14:04The Reference Implementations
- 18:53Implementation of the Tool Chain
- 27:22Shift Singly Bit Instructions
- 29:00Shift Add Instructions
- 33:56Bit Instructions
- 35:01Bit Permutation Instructions
- 37:25Generalized Shuffles
- 58:50Bit Matrix
- 1:00:4664 X 64 Bit Matrix Multiplication
- 1:01:52Transposing a 64 Times 64 Matrix
- 1:03:25Matrix-Matrix Multiply
- 1:05:33Careless Multiplier
- 1:09:43Benchmarks on Ccs
- 1:14:19Markov Fusion Recommendations
- 1:14:55Usage Examples
- 1:16:51Pack Bit Fields
- 1:23:12Compliance Test Generator
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