RISC V and Chips Alliance Address new Compute Requirements
summary
CHIPS Alliance organizes shared open-source IP and tools to cut SOC design cost by avoiding duplicate RISC‑V core work, hosting concrete projects: a VH1 superscalar core, an H2 dual‑thread upgrade and a tiny S‑EL2 microcore; cloud design‑verification using Metrics RTL simulator plus a Paris ISS golden model; Omni extend cache‑coherence over Ethernet for coherent multi‑node memory; Verilator led inside the group and a new Esperanto DRA‑Maya emulator hitting about 17 MIPS on Xeon.
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chapters (17)
- 0:00Intro
- 0:30AGENDA
- 1:03What is CHIPS Alliance?
- 2:34CHIPS Alliance - who are we?
- 3:47CHIPS Alliance - organizational structure
- 4:52Events
- 5:24Todays Compute Requirements
- 5:50Compute and Design Challenges
- 6:43CHIPS Alliance Goals and Deliverables
- 9:08Workgroups
- 10:18SweRV Core Roadmap
- 11:37Design Verification using Co-Sim with reference model
- 13:38OmniXtend Architecture Overview
- 14:20OmniXtend Reference Design
- 15:32Verilator roadmap
- 16:59BAG: Berkeley Analog Generator
- 17:30Join CHIPS Alliance
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