Andes RISC V Processor Solutions From MCU to Datacenters

on YouTube ↗22m

" summary

Andes presents a RISC-V product line spanning tiny 22/25-series MCUs to 27-series cores with a vector-capable X25V and a superscalar Fortify line running >1.1–1.2 GHz on TSMC, backed by >200 customers and >1 billion annual chips. Memory-director features boost bandwidth ~50% and halve latency versus 25-series; RVV 0.8 support with chainable functional units enables long vectors; toolchain includes a cycle-accurate simulator, vector register chaining analysis and a custom extension automated tool for SoC integration.

AI-written summary · about

" chapters (13)

1. 0:00Intro
2. 0:33Andes Corporate Overview
3. 2:01Andes V5 Architecture
4. 3:16V5 Adoptions: From MCU to Datacenters
5. 4:00V5 Adoptions: Cores in SoC
6. 4:42Andes V5 Processor Lineup
7. 6:36AndesCore™ 27 Series
8. 10:22NX27V VPU Overview
9. 12:23NX27V VPU: A Tight Loop
10. 13:29NX27V: Development Tools
11. 15:4645 Series: Performance
12. 17:49AndeSight™M: Professional IDE
13. 18:15Andes RISC-V Serving Emerging SoC from Edge to Cloud

" related talks

• 13mAndes Extended RISC V FeaturesChuan Hua Chang · 7th RISC-V Workshop 2017
• 11mDriving SoC Innovation with Synopsys RISC-V SolutionsRich Collins · RISC-V Summit Europe 2024
• 19mRISC V ISA & Foundation OverviewRick O'Conner · 8th RISC-V Workshop Barcelona 2018
• 10mAn Introduction to RISC-V Vector Programming with C IntrinsicsChih-Mao Chen · RISC-V Global Forum 2020
• 24mRISC V LLVM: Towards A Production-Ready LLVM-Based ToolchainAlex Bradbury · 7th RISC-V Workshop 2017
• 21mKeynote: RISC-V ISA: State of the UnionMark I. Himelstein · RISC-V Summit North America 2023
• 19mThe Hybrid Threading Processor for Sparse Data KernelsTony Brewer · 8th RISC-V Workshop Barcelona 2018
• 17mDemo: RISC-V Models for Verification, Software Development and Architectural Explor...Larry Lapides · RISC-V Summit 2022