Demo: RISC-V Models for Verification, Software Development and Architectural Explor...
summary
Demonstrates a configurable RISC‑V reference model and simulator that implements the full ratified spec plus stable extensions, supports vendor cores and easy custom instruction insertion, and connects to hardware verification via an open RVVI verification interface. Uses a test-driven process with about 17,000 model tests, over 250 configuration parameters, and claims 250–500 million instructions per second for virtual platform simulation. Shows DSP-style profiling to cut a hot function from ~21% to ~14–15% of execution and cites >100 organizations using the free RISC‑V OVPsimPlus.
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chapters (5)
- 0:00Start
- 4:51Imperas OVP RISC-V Models are used
- 9:36Open Virtual Platforms (OVP)
- 12:56Imperas RISC-V Processor DV Flow
- 14:47Imperas Environment for Software
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