Keynote: State of the Union
summary
RISC‑V already ships in billions of cores and vendors are delivering out‑of‑order, superscalar, vector designs that are silicon proven, mapped to newest nodes and showing ISA advantages in PPA. The spec team freezes profiles (RVA20 and RVA22, spec 0.8 on GitHub) to reduce optionality, and RVA23 is the next major release. Variable‑length instructions, modular extensions, and a common toolchain/QEMU flow are driving cores for GPUs, DSP, security and power management into a single ecosystem.
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chapters (7)
- 0:00The inevitability of RISC-V
- 1:17A shift in business models
- 2:38Designing better processors
- 6:09Unifying the SoC
- 7:54Building the best ecosystem
- 10:20Roadmap and standards
- 16:36Conclusion and summary
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