RISC-V FutureWatch - Microchip: RISC-V based Mid-range FPGAs: Fueling The Edge Comp...
summary
Microchip ships the PolarFire SoC with a hardened RISC‑V MSS (production samples June/July) and claims twice the power efficiency of competing mid‑range FPGAs; PolarFire2 promises to double that efficiency again while boosting TOPS/sec by about 15x when RISC‑V compute engines are combined. A 2 MB configurable L2 cache enables independent real‑time vs Linux contexts, a radiation‑tolerant variant flies in space, and a new C++‑friendly design suite plus 62 myFive partners round out the ecosystem.
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chapters (13)
- 0:00Introduction
- 2:02Retrospective
- 8:23Polar Fire
- 10:38Freedom to innovate
- 12:59Independent Software Context
- 13:42Power is Money
- 15:10Ecosystem
- 16:18Edge Compute
- 17:25AI Machine Learning
- 22:03Bridge the gap
- 23:24New tools
- 24:17Traditional FPGA design
- 24:55Conclusion
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