Keynote: HPSC – Radically Advancing the Capabilities of Space-based Computing
summary
HPSC is a NASA–JPL–Microchip RISC‑V program delivering a multi‑core SoC plus boards, firmware and software; prototypes arrive calendar 2024 and space‑qualified products in 2025. It uses SiFive x280 clusters (two clusters of four cores = eight application cores) with a vector engine that shows >1000× speedup on the math‑heavy SpaceBench emulator, supports FPGA/GPU offloads, TSN TSN Ethernet networking, ECC/TMR fault tolerance, and dynamic power scaling across more than two orders of magnitude.
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chapters (13)
- 0:00Overview of HPSC
- 4:26Guiding design principles
- 4:54Architecture and performance
- 7:32Project roadmap and market
- 8:08Autonomy in space missions
- 9:58NASA's strategic framework
- 11:07Decadal study alignment
- 12:38Data processing needs
- 13:23Technical capabilities
- 15:41Layered fault tolerance
- 16:04Ethernet and networking
- 16:48Ecosystem and future growth
- 17:26Conclusion
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