Akeana : Breaking Performance Barriers
Talkat RISC-V Summit North America 2024 · on Wednesday, 2024-10-23· at 15:20· Expo Hall - Exhibit Hall A - Demo Theater·
summary
Akeana presents RISC‑V IP claiming high throughput and production readiness: 25 SPECint for the 5000 family, a 32‑bit 100 series, midrange 1000 series, and a flagship 5000 series targeting Neoverse N2/N3 performance. Hardware suite includes vector extensions to 2K vector length, matrix AI accelerators, and a coherent fabric that scales to thousands of cores. Emulation runs on HAPS and Cadence Palladium, and a third‑party test suite reports zero errors; custom core and PPA optimizations cut area/power by ~30%.
AI-written summary · about
chapters (9)
- 0:00Introduction to Akeana
- 1:04About Akeana company
- 3:53Akeana processor IP families
- 5:18Performance breakthrough with 5000 series
- 6:26System IP and accelerators
- 7:32Interconnect fabric capabilities
- 8:39Software and emulation support
- 10:24Customization and case study
- 11:47Summary and key benefits
related talks
12mDemo: Akeana: Highest Performance, Customized Cores, Multi-core/Multi-thread Clusters-
18mRISC-V Performance Delivered
15mRISC-V CPUs for the New Era of Heterogeneous Computing
17mKeynote: Racing to Adoption: From Momentum to Mainstream with RISC-V
37mKeynote: RISC-V Launchpad Showcase
15mRISC-V processor IP product line
14mRISC-V Grows Up and Goes Big!
15mSyntacore RISC-V IP
