Open-Source Commercial-Grade RISC-V IOMMU with Verification

on YouTube ↗19m

" summary

Open-source, parameterizable RISC‑V IOMMU IP implements SV39 single and two‑stage translation, superpages, MSI translation modes, IO Address Translation Caches, AXI interfaces and a translation block with memory walkers; it runs on FPGA (booting Linux, used in AlSaqr 2.0 and PULP Carfield) and exposes a register/queue software interface. Verification by 10xEngineers uses Jasper formal and UVM simulation, finds ~10 RTL bugs per unit in months, achieves ~91–92% and ~83% unit coverage, aims for ~95% code coverage and 100% functional coverage, and reports formal bug‑hunt rate ~2× simulation.

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" chapters (7)

1. 0:00Introduction to IOMMU
2. 1:28RISC-V IOMMU development
3. 3:16Architectural features
4. 4:34Microarchitecture overview
5. 6:25Verification methodology
6. 11:58In-context validation
7. 14:12Q&A and concluding remarks

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