I/O Virtualization Use Cases and the RISC-V IOMMU Overview
summary
RISC-V IOMMU implementation provides two-stage address translation so devices can be passed to VMs using guest→supervisor mappings, and it supports address translation cache (ATC) plus a centralized page-table walker to avoid ~20 memory accesses per I/O. Built features include a memory‑mapped command queue for invalidations, a page request queue for recoverable faults and device-side translation fetch, and integration points for VFIO and PCIe ATS/CXL. Covers dedicated vs shared IMMU placements and links to the GitHub IMMU spec.
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chapters (11)
- 0:00Intro
- 0:27Device Memory Access
- 2:34IOMMU address translation and protection
- 5:00Memory Virtualization
- 6:10Two-stage address translation
- 7:14Address Translation Caching
- 8:56Fault reporting
- 10:34Recoverable faults
- 12:44Integration models
- 14:01Software frameworks.
- 14:52Summary
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