MiniFloat-NN: A RISC-V ISA Extension for Low-Precision NN Training
summary
Extension implements widening sum-of-dot-products and three-term additions in a parameterized FP unit integrated into an open-source RISC‑V FPU and Snitch cluster, supporting two 16-bit and two 8-bit FP formats with stochastic rounding as a new mode. Fabricated in 12 nm at 1.2 GHz, the module adds ~15% cluster area, runs twice the work per cycle for expanding FMAs, and delivers up to a 7.2x efficiency increase over FP64 while preserving mixed‑precision accumulation.
AI-written summary · about
chapters (8)
- 0:00Introduction and motivation
- 3:02Architecture design strategy
- 4:46Mixed precision methodology
- 7:23Instruction set extensions
- 8:51Functional unit implementation
- 10:43Cluster integration and area
- 12:28Performance benchmarks
- 14:24Vector processor and conclusion
related talks
10mSupport TVM QNN Flow on RISC-V with SIMD Computation
26mLow-Precision Inference without Quality Loss...
14mLow-Cost SIMD Module for ML Acceleration
28mAn Efficient Implementation of TensorFlow Lite for RISC-V Vectors
15mPushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC...
26mExploring HiFloat8: A Tapered Format Complementing the FP8 Ecosystem for Robust Model T...
19mRISC-V: Changing the Way AI/ML Accelerators and Computing Infrastructure Are Built
24mEnhancing Transformers: Accelerating Nonlinear Function Computation On RISC-V Vector Processor