RISC-V FutureWatch: MIPS - Bringing a New Level of Scalability to RISC-V - MIPS eVoco...
summary
MIPS unveils the MIPS eVocore P8700, an out‑of‑order, multi‑threaded RISC‑V core that claims industry‑leading single‑ and dual‑thread performance, a coherent fabric and scales to over 500 cores in multi‑cluster systems. Targeted at ADAS/automotive, it includes safety features to speed certification and an FPGA SDK for early software bring‑up; a major ADAS vendor (Mobileye) is committing the P8700 to its next SoC, so silicon and customer integrations are already underway.
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chapters (9)
- 0:00Introduction to MIPS RISC-V
- 1:26Scalable high performance
- 3:14Adopting RISC-V architecture
- 5:51Automotive market shift
- 8:57The p8700 processor core
- 10:48Mobileye partnership
- 13:46Performance and efficiency
- 16:05Safety and development tools
- 19:05Conclusion and Q&A
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