Proving RISC-V Security Model Compliance with SESIP

on YouTube ↗18m

" summary

Shows how SESIP maps the RISC‑V Platform Security Model to a reusable catalog of security features and a corresponding C1–C5 evaluation levels regimen that increases verification effort from document review to white‑box pentesting; assessment focuses on remote attacks by default with optional physical‑attack claims. Component evaluations get combined via component result reuse so a RISC‑V root‑of‑trust can be assessed once, integrated with others, and NXP reports applying the profile to its RISC‑V products with certificates accepted by PSA Verified for RFC 8259A.

AI-written summary · about

" chapters (13)

1. 0:00Intro
2. 0:32Context-loT security ecosystem complexity
3. 1:26Context - compliance demonstration needed
4. 2:43Security platform's role in device security requirements
5. 3:45Challenge - compliance demonstration comple
6. 5:16What SESIP brings
7. 6:43SESIP composition and reuse details
8. 7:35Mappable and accessible security features
9. 9:29Adapted attack contexts
10. 10:45RISC-V & SESIP mappability overview
11. 12:39Relevant security leveling
12. 14:36Core MCU/MPU SESIP Profile
13. 16:23Conclusion

" related talks

• 25mRISC V and Meta framework Security Cert Approach for a Secure Connected WorldJohn Boggie · RISC-V Summit 2019
• 13mRISC-V: Securing the Future of Open Source ComputingAndrew Dellow · Spring 2022 RISC-V Week — RISC-V International Day
• 19mAn Open Source Approach to System SecurityHelena Handschuh · RISC-V Summit 2019
• 18mCPU Security in the Context of RISC-VKarthik Raj Shekar · RISC-V Summit North America 2024
• 45mVerified seL4 on secure RISC-V processorsGernot Heiser · linux.conf.au 2020
• 16mKeynote: RISC-V Security - Current Initiatives and Future TrendsHelena Handschuh · RISC-V Summit North America 2024
• 09mThe Future of Embedded Security with RISC-VDavid Kerr-Munslow · RISC-V at embedded world 2024
• 21mRISC-V International Security OverviewHelena Handschuh · RISC-V Forum: Security 2021