Keynote: RISC-V Security - Current Initiatives and Future Trends
Talkat RISC-V Summit North America 2024 · on Wednesday, 2024-10-23· at 09:20· Mission City Ballroom B2 - B5 (Level 1)·
summary
Argues that secure AI-era platforms require a hardware root of trust, measured boot, trusted execution environments with hardware attestation, secure key management and post-quantum algorithms (NIST FIPS 203/204/205); lists ratified RISC-V work such as scalar/vector crypto and control‑flow integrity plus ongoing specs for domain isolation, EPMP/SPMP and memory tagging; highlights OpenTitan open-source root of trust, masked implementations, timing fences and CHERI/“Cherry” memory-safety efforts and calls for secure supply chains and formal verification.
AI-written summary · about
chapters (6)
- 0:00The need for cybersecurity
- 3:00Essential security components
- 6:21RISC-V security initiatives
- 9:01Implementation security
- 10:08Industry and academic updates
- 14:04Future security trends
related talks
13mRISC-V: Securing the Future of Open Source Computing
16mKeynote: NVIDIA’s secure RISC-V processor
19mAn Open Source Approach to System Security
45mThe Future of Security is in Open Silicon
14mKeynote: Blockchain, Cryptography, and RISC-V: A New Frontier in Open Development
09mThe Future of Embedded Security with RISC-V
21mRISC-V International Security Overview
50mProgress in Standardizing Cryptography Extensions for RISC-V Processors
