Load/Store Pair for RV32 (Zilsd & Zclsd)
summary
Zilsd & Zclsd add RV32 load/store pair instructions by reusing RV64 doubleword encodings and compressed forms, allowing two-register aligned 64-bit accesses; implementations can be nonatomic on 32-bit buses or single-cycle on 64-bit data interfaces. Evaluation uses LLVM and Spike (GCC prototype exists) and shows up to 25% static code-size savings on double-heavy benchmarks, about 1.76% average across mixed suites, and 15%+ instruction-retired reduction where workloads fit; specification is near ratification.
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chapters (7)
- 0:00Introduction and overview
- 1:50Background and motivation
- 3:21Technical design details
- 4:34Design considerations
- 8:44LLVM benchmarking results
- 14:25GCC implementation and results
- 15:31Conclusion and Q&A
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