Simultaneous Multithreading with RISC-V Enables Higher Throughput Efficiency in Data-Centric Applications in Automotive
Talkat RISC-V Summit North America 2024 · on Wednesday, 2024-10-23· at 14:55· Grand Ballroom H (Level 1)·
summary
Claims a RISC‑V SMT core design for automotive sensor‑fusion and zonal/HPC use that ships in MIPS products and runs 2 or 4 hardware threads per core, targeting interrupt‑heavy pipelines and AI accelerators. Measured benefits include 20–30% efficiency gain on interrupt‑heavy sensor‑fusion workloads and up to a 2x cycle reduction for low‑latency real‑time tasks, with lower area, cost and cooling needs and a roadmap to chiplet scaling.
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chapters (10)
- 0:00Introduction to MIPS automotive
- 1:49Automotive market challenges
- 4:28Automotive architecture overview
- 7:00Performance and sensor scaling
- 8:28Typical design flaws and solutions
- 13:50Simultaneous multithreading
- 16:07Beyond Moore's Law
- 16:46Scaling with chiplets
- 17:13Conclusion and summary
- 17:48Q&A session
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