Bridging the Gap: Compiling and Optimizing Triton Kernels Onto RISC-V Targets Based on MLIR
Talkat RISC-V Summit North America 2024 · on Tuesday, 2024-10-22· at 14:55· Grand Ballroom G (Level 1)·
summary
An end to end stack lowers Triton kernels and PyTorch/ONNX/TensorFlow/JAX graphs into MLIR (linalg/tensor/vector/scf) and then LLVM to target RISC‑V, with a Triton→MLIR front end, Eray-based graph mapping and kernel+graph fusion. Benchmarks on an RV64 platform show Triton kernels match C in many cases, beat C for matmul by 15–40%, and improve layer‑norm single‑thread by ~133%; multicore scaling stalls past four threads from memory bandwidth. Planned work adds a Triton-aware MLIR backend and broader autotiling/auto‑vectorization.
AI-written summary · about
chapters (5)
- 0:00Motivation and agenda
- 0:26Triton for RISC-V overview
- 4:17Triton basics
- 25:28Future compiler direction
- 33:15Summary and conclusion
related talks
25mRace to Superintelligence: Building Low-Friction AI Infrastructure for a Heterogen...
08mGPU Programming with Triton Kernels
22mEnabling VLLM V1 on AMD GPUs With Triton
16mLightning Talk: Triton Compiler
10mMaximizing Kernel Development Productivity Under Performance Constraints
24mPortable High‑Performance LLM Serving: A Triton Backend for...
25mLeveraging AI Ecosystem for Portable and Sustainable GPU Kernels in HPC
23mEmpower Upstream ML Frameworks on RISC-V