~/talk

Demo: XuanTie RISC-V Hardware and Software Full-stack Technology

name:James Shi
links:none on file
slides:none on file

Demonstrates XuanTie (Shen) full-stack IP: C-series C920/C930 application cores, R98 real-time automotive core, and E-series microcontroller, plus tooling that autogenerates compiler, ISA simulator and profilers from a customer-defined DSA. Claims AI stack optimizations for TensorFlow/PyTorch/Caffe with SHL runtime yielding up to 7x edge and up to 17.5x large-model speedups, and a C930 delivering over 15 SPECint2006 per GHz single-core. Adds hypervisor and scalable IOMMU two-stage translation, and a confidential computing bundle: domain manager, memory encryption engine, and memory-tracking table.

AI-written summary · about

  1. 0:00Introduction to XuanTie RISC-V
  2. 1:46Key challenges for RISC-V
  3. 3:50ShenTie’s solutions overview
  4. 4:36Shen DSA integration solution
  5. 6:49AI acceleration with vectorization
  6. 8:15Virtualization and security solutions
  7. 10:48Shen CPU lineup overview
  8. 12:36Future of RISC-V and closing
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