Keynote Panel: The Future of High Perfor...
summary
RISC‑V is already powering diverse HPC experiments: TensTorrent cards and Thunderbird accelerators appear in demos, a Banana Pi runs AI workloads, and a claim of ~1,000,000 embedded RISC‑V cores inside top systems highlights scale. The concrete gains are large vector units for data‑parallel kernels, tightly coupled accelerators using MPI‑style messaging for low‑latency offload, and RISC‑V enabling a quantum‑control board to be programmed in C instead of bespoke firmware. Remaining gaps are mature libraries, high‑quality CPU implementations and power‑efficient silicon.
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chapters (17)
- 0:00Welcome and panel intro
- 2:55Why HPC is exciting for RISC-V
- 5:46HPC and ISA challenges
- 7:53Redefining high performance computing
- 9:59Flexible HPC platform design
- 12:29RISC-V enabling new HPC capabilities
- 15:58Openness and architectural diversity
- 17:24Vector extensions and HPC needs
- 19:10Heterogeneity and specialization in HPC
- 21:43AI and HPC convergence
- 26:42Legacy software and ecosystem challenges
- 28:26Software ecosystem and standardization
- 31:12Open RISC-V and HPC development
- 33:01RISC-V in top supercomputers
- 33:42Sovereign compute initiatives
- 35:52Blocking factors for RISC-V adoption
- 39:30Closing remarks and next steps
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