RISC-V: Enabling Open Physical AI
summary
Argues RISC-V hardware and software enable practical “physical AI” by combining ISA extensions, tightly coupled accelerators and large latency-tolerant clusters to close the energy gap — ISA/domain-specific extensions give >10× speed and energy, stacking tightly-coupled and fully-specialized engines yields up to 4 orders of magnitude total; uses Spatz vector units and DMA/tensor copy engines for multi-stage latency hiding and presents Picobello, a Picobello 7nm test chip with 16 tiles in the EuroHPC U‑Pilot showing the concepts work but noting chiplet packaging yields remain immature in Europe.
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chapters (24)
- 0:00Introduction to RISC-V
- 0:25What is physical AI
- 3:00Why RISC-V for AI
- 4:23Moore's law efficiency gap
- 5:07Brain-inspired architecture
- 6:53Domain-specific ISA extensions
- 8:19Multi-core parallel execution
- 9:43RISC-V acceleration spectrum
- 10:45Four orders of energy efficiency
- 12:35Open software ecosystem
- 13:17Agentic reasoning in AI
- 15:08LLM inference challenges
- 16:32Patterson's Law and roofline
- 17:57Latency tolerance architecture
- 19:20Memory latency hiding
- 20:24Little's Law and buffering
- 21:06MemPool and TeraPool concept
- 21:48TensorPool specialization
- 23:10Global interconnect design
- 24:35Picobello chip overview
- 25:38GenAI specialized NOC
- 26:22Scaling with chiplets
- 27:23Summary and future work
- 27:56Q&A session
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