ARBEL™ The Leading Server-Class RISC-V CPU
summary
Next Silicon shows working silicon and a roadmap: test chip: dual‑core 2.4 GHz with PCIe CXL and PCIe Gen5 IO, 2 MB L3 per home node, runs Ubuntu and GCC/LLVM as a mini‑PC and server chiplet: 64 cores, three 256‑bit vector units, big caches, DDR5 or LPDDR6 SKUs and PCIe Gen6 I/O. Cycle‑accurate simulator matches silicon, benchmarks include STREAM, CoreMark and SPEC CPU, and company projects SPEC ratios of ~2.6 (INT) and ≥3.4 (FP) per GHz.
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chapters (12)
- 0:00Introduction to Next Silicon
- 1:42Next Silicon's Vision
- 2:57Choosing the RISC-V Path
- 4:16Evolution of Arbel Goals
- 4:54Development Generations
- 6:17The Arbel Test Chip
- 6:51Test Chip Performance Demo
- 8:16The Future Arbel CPU
- 8:40Arbel Architecture Specs
- 9:46Core Innovation and Metrics
- 14:08Scalability and Closing
- 14:33Final Summary
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