State of the Union
summary
State of RISC‑V is strong: RVA23 ratified Oct 2024 and vendor silicon appears in 2026, under a ratified server platform spec, but parity with incumbents needs several generations and software tuning on real hardware. Standards add two optimization guidance options: OILSM (fast misaligned) and OIV_OVLT (vector rate) to align HW/SW performance. Matrix work advances with four matrix extension approaches (batch dot, IME, VME, AME) nearing ratification, while security, DSP and long‑instruction efforts make steady progress.
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chapters (13)
- 0:00Introduction and welcome
- 1:05RISC-V adoption in embedded and AI
- 2:49RISC-V servers and RVA23 progress
- 6:01Optimization guidance options for performance
- 9:57Matrix extensions for AI compute
- 12:01Evolution of AI compute architectures
- 17:57RISC-V’s modularity for AI workloads
- 18:17Security extensions in RISC-V
- 20:43DSP and vector extensions
- 21:47Microcontroller profiles and standardization
- 23:54Long instruction group and future ISA
- 25:38Summary and 2026 outlook
- 26:20Q&A session
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