Demo: RISC-V as an Enabler of Heterogeneous Compute
Talkat RISC-V Summit North America 2023 · on Wednesday, 2023-11-08· at 12:35· Expo Hall - Exhibit Hall A - Demo Theater·
summary
Codasip studio customizes an L31 RISC-V core in Codal, adds three ISA extensions and shows they actually improve real code. The LLVM-based toolchain regenerates SDK and RTL, the compiler auto-selects the new multi-accumulate instruction (one-cycle MAC) cutting a FIR filter from 17K to ~15K cycles, then a 20-line post-increment loads/stores change shaves more cycles, and a tiny bit-reverse instruction replaces a 40K-cycle routine with ~3K. All changes compile, profile, and run.
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chapters (7)
- 0:00Introduction to demo
- 1:03Company and technology overview
- 5:36Demo setup and profiling
- 7:00Adding MAC instruction
- 8:49Post-increment load/store
- 10:14Bit reverse instruction
- 12:22Conclusion and benefits
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