Designing Next Generation 5G Wireless Infrastructure Using RISC-V

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" summary

LeapFrog presents a tile/chiplet architecture of clustered LPUs — a sea of RISC-V cores with a custom ISA and vector/matrix units that implement L1 plus optional L2/L3 on-chip. Claim shows 10x performance/W/cost versus legacy RAN and Intel FlexRAN, and power targets of about a third of typical embedded base stations (and under 0.1x versus FlexRAN). Design scales from small cells to mMIMO, supports disaggregated or inline L1, and is demoed with Ventana compute chiplets and a Mamer productization path.

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" chapters (14)

1. 0:00Introduction to LeapFrog
2. 1:06Team and background
3. 2:10Market drivers for 5G
4. 3:54Challenges in 5G infrastructure
5. 4:57RISC-V-based chiplet architecture
6. 6:20AI-enhanced wireless processing
7. 7:24LeapFrog Processing Unit design
8. 8:45Disaggregating layer one
9. 9:47Power efficiency and DU/CU integration
10. 10:50Open RAN and integration models
11. 11:55Software stack overview
12. 12:56Go-to-market strategies
13. 13:59Applications beyond wireless
14. 14:22Summary and Q&A

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