Preparing for a Valid Performance Evaluation of RISC-V AP, in the Mobile Space
summary
Built a RISC‑V application processor into an SoC emulator with a full software stack and run Geekbench 5 over an ART interface, initially measuring about 60% of target performance versus comparable ISAs. Systematic fixes — enabling ISA extensions in compilers, swapping in optimized libraries, and adding hand‑tuned intrinsics for AES and ML — raise most workloads by ~10–30% and some image kernels by 2x, with hot paths reaching up to a 20x boost, proving software optimization, not silicon, drives the gap.
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chapters (6)
- 0:00Samsung's RISC-V journey
- 3:23Engineering challenges
- 6:45Performance validation setup
- 9:28Analyzing performance gaps
- 12:38Optimization strategies
- 14:45Conclusion and Q&A
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