Demo: STING Design Verification: A Robust Approach for Complex RISC-V CPU and SoC Validation

on YouTube ↗14m

" summary

STING is a RISC‑V verification suite with a random+directed stimulus engine, a STING Configuration Creator (SEC) that derives DUT/board parameters from a single spec, and a snippet programming framework that injects hooks and weak functions for custom extensions and interrupt/NMI handlers. It ports RV litmus tests, includes cache colliders, register sweeps and branch‑harass workloads, and offers four checkers—signature, model‑reference, multipass, and directed checks—while generating hundreds-to‑thousands of tests in a single ELF for sim/emulation/post‑silicon runs.

AI-written summary · about

" chapters (7)

1. 0:00Introduction to Sting
2. 1:10Verification challenges
3. 2:42Configuration and management
4. 4:43Snippet programming framework
5. 8:24Methodologies and workloads
6. 11:06Checking and portability
7. 13:29Future outlook and summary

" related talks

• 24mRISC V Processor Verification based on Open source FrameworkLee Moore, Richard Ho · RISC-V Summit 2019
• 23mOpen Source Verification Platform for RISC V ProcessorsTao Liu, Richard Ho · RISC-V Summit 2019
• 13mIntroduction to RISC-V Processor VerificationLarry Lapides · embedded world 2022
• 46mRISC-V Open ISA’s Shock Wave of Processor Innovation Causing Seismic ShiftMike Thompson, Simon Davidmann, Ann Mutschler, Richard Ho, Emerson Hsiao, Dave Kelf, Frank Schirrmeister · RISC-V Summit 2019
• 23mThe Continuum of RISC-V Compliance and Verification TestingSimon Davidmann, Allen Baum · RISC-V Summit 2022
• 47mTutorial: Choosing Appropriate Verification Techniques for Desired RISC...Aimee Sutton, Lee Moore · RISC-V Summit 2022
• 53mRISC-V Architectural Certification Tests Early Adoption WorkshopDavid Harris, Jordan Carlin · RISC-V Summit Europe 2026 Developer Workshops
• 15mThe RISC-V Verification Ecosystem with Open Standards and Commercial ToolsJon Taylor · RISC-V Summit Europe 2023